FIG. 1 shows an example of a conventional electrical package for high-end servers. Electrical package 10 includes organic substrate 1, semiconductor chip 2 electrically connected to the organic substrate using a plurality of solder balls (bumps) 3, lid 4 for encapsulating semiconductor chip 2 on organic substrate 1.
In FIG. 1, the inner surface of the central part of lid 4 is connected to the surface of semiconductor chip 2 via TIM 5. The inner surface of the outer part of lid 4 is hermetically connected to the surface of organic substrate 1 using sealing materials 6. Further, underfill 7 is formed between semiconductor chip 2 and the surface of organic substrate 1.
Since the coefficient of thermal expansion (CTE) of each component in package 10 is different, thermo-mechanical stress occurs within package 10, and also warpage of organic substrate 1 occurs during the thermal cycle/stress. As a result, delamination of TIM 5 tends to occur, especially in corner part 8. When the TIM delamination occurs, the temperature of semiconductor chip 2 increases because of insufficient cooling performance, and semiconductor chip 2 may not operate properly.
Therefore it is necessary to reduce the TIM delamination occurred under the thermal cycle/stress in order to maintain the semiconductor chip performance/reliability.